Agenda - オンライン Video On Demand
事前登録 / Registration

Date: Monday, November 18, 2024

Plenary Session
Welcome and Opening Remarks
TSMC Keynote & Guest Speech

Included All In-Person Papers

HPC & 3DFabric Track

3Dblox 3.0 – maximizing 3DIC design productivity from feasibility to 3D global resource optimization

TSMC

AMD and Cadence collaborate to streamline and automate routing of multi-chiplet TSMC 3DFabric technologies

Cadence/AMD

Effective methods to reuse and automate bump creation for chiplets in 3DIC designs

Synopsys/AMD

Electro-Thermal Modeling and Simulation for Thermal Management in Co-Packaged Optics

Cadence

Simplifying requirements and flows of SoIC technology for Stacked die design with TSMC 3Dblox and Cadence Integrity 3D-IC Platform

Cadence/GUC

Multi-die design for TSMC COUPE with unified electronic and photonic design solutions

Synopsys/Ansys

Efficient 3D Chiplet Stacking Using TSMC SoIC Technology

Alchip/Synopsys

Distributed and GPU-accelerated 3D EM Simulations for IC and 3DIC Silicon Photonics Applications with Peakview

Lorentz Solution/NVIDIA

3DIC Physical Implementation and SoIC-X Silicon Testing Results

GUC

Architecting next generations Terabit AI networks with Industry’s First Multi-Protocol I/O Connectivity Chiplet

Alphawave Semi

Design of vertical fiber-to-chip coupling system in TSMC’s COUPE Silicon Photonics platform for Co-Packaged Optics and In-Package Optical I/O applications

Ansys

Realizing benefits of Backside Power and Clock on TSMC A16 technology node

Synopsys

Thermal modeling of backside power delivery structure –- a N2 process case practice

Ansys

Leveraging TSMC’s CoWoS Interposer and Synopsys’SLM IP to Monitor, Test, and Repair Multi-Die Designs

Synopsys/TSMC

Ansys-Synopsys-TSMC Solve the 3DIC Multiphysics Challenges

Synopsys/Ansys

Die-to-Die Physical-Aware Interconnect Testing Using 3Dblox For Reduced Manufacturing Test Cost

Siemens DI SW/TSMC

HBM3/HBM3E Implementation Challenges When Integrating Memory Controllers with Physical Layer Solutions, and How to Overcome them

Rambus/Cadence

TSMC A16 backside power delivery EMIR enablement with an innovative standard cell power modeling method

Ansys

Addressing 3DIC Design Reliability Challenges with a Cutting-Edge Mechanical Stress Modeling and Simulation Approach

Cadence

Thermal challenges and an innovative solution for 3D heterogeneous integration of Co-Packaged Optics

ANSYS INC.

Insights into the Synopsys-TSMC UCIe IP on N5 and CoWoS Test Chip

Synopsys
Mobile, IoT & Automotive Track

AI-powered EDA solutions for better design PPA, QoR and productivity

TSMC

AI-Driven Analog Design Migration Solution Tuned for TSMC Technology Platforms

Synopsys

Leveraging AI/ML as the next leap to custom design automation

Cadence/Renesas

New approach that targets EM/IR hotspot analysis and fixing with mPower and Calibre DesignEnhancer

Siemens EDA/MediaTek

Realtime Safety Monitoring for Automotive Electronics based on Deep Data

proteanTecs

A comprehensive IP validation methodology for Microsoft’s AI and high-performance compute chips

Siemens EDA/Microsoft

Enabling a Battery-Free IoT Future: Sofics and ONiO Collaboration on Ultra-Low Leakage ESD Protection

Sofics/ONiO

A highly parallelizable Time Dependent Dielectric Breakdown (TDDB) solution readiness for TSMC automotive platform

Ansys

Soft Error Simulation Tool to Create an N3E SER Library

IROC Technologies

Low-Power Communication IC Design Verified by AI-Powered Simulation Flow

Siemens EDA/THine Electronics

Smart Optimization and Timing Closure for Automotive Designs-Block Level to Full-Chip

Cadence/Renesas

Improve design closure by 10X with Quantus Insight at Advanced Nodes

Cadence/CelestialAI

2.5D/3DIC ESD Reliability Analysis

Ansys Inc

AI Driven Layout Optimization For T-Coil Matching Networks

Ansys/AMD

Innovative ESD Protection Solutions at 3nm FinFET: A Partnership Between Sofics and Siemens EDA

Sofics/Siemens EDA

AI-based RF design synthesis flow

Synopsys

Mastering the Timing Closure Maze for Enhanced Productivity and Efficiency with Tempus & Certus

Cadence/Intel

Groundbreaking SRAM Repair Toolset: Pre-integrated Siemens Tessent MBIST with eMemory’s NeoFuse OTP

eMemory/Siemens EDA

Enabling SoC Scaling to GAA Processes with Synopsys Foundation IP

Synopsys

LLM Based Physical Verification Runset Generator

Synopsys

* 講演時間、プログラム等は、変更になる場合がございます。

Legal Notice

TSMC is not responsible for the content, accuracy, or reliability of any of the presentations at the TSMC Open Innovation Platform Ecosystem Forum. Furthermore, posting the presentation abstracts on TSMC's corporate website does not constitute an endorsement of the content of those presentations by TSMC. Any liability arising from the contents of any of the presentations is the responsibility of the presenter itself, and not TSMC.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.