Agenda - オンライン Video On Demand
Date: Thursday, November 6, 2025
| Plenary Session | ||
| Welcome and Opening Remarks | ||
| TSMC Keynote & Guest Speech | ||
Hierarchical EM-IR Signoff Methodology for large SoCs integrated in 2.5DIC Structures
Accelerating AI Infrastructure Performance
Achieving 3D-IC Chiplet Security through CoWoS, Starting with PUF-Based OTP and HRoT
Extending the Usage of Die-to-Die (D2D) UCIe for AI Custom Silicon Use Cases
M31 Ultra-low power solution on TSMC N6e Platform: Powering Edge AI and AIoT applications
Liberty IP Excellence: Building a Robust Verification Framework for automotive IPs
GDDR Memory for High-Performance AI Inference
Unlocking Maximum PPA on TSMC N2/N2P with Strategic Design and Technology Synergy
Advanced Cross-PDK library comparison and verification for SerDes production
From Block, Chip to System: A Comprehensive flow for large FPGA Dynamic Power Integrity Sign-off
Accelerating SRAM Design Cycles With Additive AI Technology
* 講演時間、プログラム等は、変更になる場合がございます。
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The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.