TSMC OIP Ecosystem Forum

Date: Friday, October 25, 2024

Time	Plenary Session
08:30 - 09:30	Registration & Ecosystem Pavilion
09:30 - 09:45	Welcome and Opening Remarks
09:45 - 10:30	TSMC Keynote & Guest Speech
10:30 - 11:00	Coffee Break & Ecosystem Pavilion
11:00 – 11:30	3Dblox 3.0 – maximizing 3DIC design productivity from feasibility to 3D global resource optimization TSMC	AI-powered EDA solutions for better design PPA, QoR and productivity TSMC
	HPC & 3DFabric Track	Mobile, IoT & Automotive Track
11:30 – 11:50	AMD and Cadence collaborate to streamline and automate routing of multi-chiplet TSMC 3DFabric technologies Cadence/AMD	AI-Driven Analog Design Migration Solution Tuned for TSMC Technology Platforms Synopsys
11:50 – 12:10	Effective methods to reuse and automate bump creation for chiplets in 3DIC designs Synopsys/AMD	Leveraging AI/ML as the next leap to custom design automation Cadence/Renesas
12:10 – 12:30	Electro-Thermal Modeling and Simulation for Thermal Management in Co-Packaged Optics Cadence	New approach that targets EM/IR hotspot analysis and fixing with mPower and Calibre DesignEnhancer Siemens EDA/MediaTek
12:30 – 13:30	Lunch & Ecosystem Pavilion
13:30 – 13:50	Simplifying requirements and flows of SoIC technology for Stacked die design with TSMC 3Dblox and Cadence Integrity 3D-IC Platform Cadence/GUC	Realtime Safety Monitoring for Automotive Electronics based on Deep Data proteanTecs
13:50 – 14:10	Multi-die design for TSMC COUPE with unified electronic and photonic design solutions Synopsys/Ansys	A comprehensive IP validation methodology for Microsoft’s AI and high-performance compute chips Siemens EDA/Microsoft
14:10 – 14:30	Efficient 3D Chiplet Stacking Using TSMC SoIC Technology Alchip/Synopsys	Enabling a Battery-Free IoT Future: Sofics and ONiO Collaboration on Ultra-Low Leakage ESD Protection Sofics/ONiO
14:30 – 14:50	Distributed and GPU-accelerated 3D EM Simulations for IC and 3DIC Silicon Photonics Applications with Peakview Lorentz Solution/NVIDIA	A highly parallelizable Time Dependent Dielectric Breakdown (TDDB) solution readiness for TSMC automotive platform Ansys
14:50 – 15:20	Coffee Break & Ecosystem Pavilion
15:20 – 15:40	3DIC Physical Implementation and SoIC-X Silicon Testing Results GUC	Soft Error Simulation Tool to Create an N3E SER Library IROC Technologies
15:40 – 16:00	Architecting next generations Terabit AI networks with Industry’s First Multi-Protocol I/O Connectivity Chiplet Alphawave Semi	Low-Power Communication IC Design Verified by AI-Powered Simulation Flow Siemens EDA/THine Electronics
16:00 – 16:20	Design of vertical fiber-to-chip coupling system in TSMC’s COUPE Silicon Photonics platform for Co-Packaged Optics and In-Package Optical I/O applications Ansys	Smart Optimization and Timing Closure for Automotive Designs-Block Level to Full-Chip Cadence/Renesas
16:20 – 17:30	Closing Reception

* 講演時間、プログラム等は、変更になる場合がございます。