TSMC OIP Ecosystem Forum

Date: Friday, October 24, 2025

Time	Plenary Session
08:30 - 09:30	Registration & Ecosystem Pavilion
09:30 - 09:45	G-1Welcome Remarks
09:45 - 10:00	G-1Guest Speech
10:00 - 10:30	G-1TSMC Keynote
10:30 - 11:00	Coffee Break & Ecosystem Pavilion
11:00 – 11:30	G-2 Building Tomorrow’s AI Systems with Advanced 3D IC Design Solutions TSMC	G-3 Automotive Platform for Accelerating AI in Future Software and Silicon-Defined Vehicles TSMC
	HPC & 3DFabric Track	Mobile, IoT & Automotive Track
11:30 – 11:50	A-1 Optmized automated routing flow for 3DIC to streamline substrate layout generation Cadence/AMD	B-1 Power-Aware DFT - Taming IR-Drop for Robust Automotive SoC EMIR Sign-off NXP Semiconductors/Ansys
11:50 – 12:10	A-2 Hierarchical EM-IR Signoff Methodology for large SoCs integrated in 2.5DIC Structures Annapurna Labs US/Ansys	B-2 Analog Design Migration and Optimization Flow Cadence
12:10 – 12:30	A-3 Accelerating AI Infrastructure Performance Alchip Technologies/Ayar Labs	B-3 Extending the Usage of Die-to-Die (D2D) UCIe for AI Custom Silicon Use Cases Alphawave Semi/Keysight
12:30 – 13:30	Lunch & Ecosystem Pavilion
13:30 – 13:50	A-4 Thermal Aware Design Optimizations and Signoff Using RHSC Electrothermal across Process Nodes/Design NVIDIA/Ansys	B-4 M31 Ultra-low power solution on TSMC N6e Platform: Powering Edge AI and AIoT applications M31 Technology
13:50 – 14:10	A-5 Advanced Packaging Technologies for Modular and Powerful Compute GUC	B-5 Renesas has successfully adopted Pegasus DRC on TSMC 3nm process Automotive SoC Cadence/Renesas
14:10 – 14:30	A-6 Breaking the Bandwidth Barrier: Enabling Celestial.AI’s Photonic Fabric™ with Custom ESD IP on TSMC’s 5nm Platform Sofics/Celestial AI	B-6 Meeting SRAM and Foundation IP Requirements for Next-Generation Automotive SoCs on 5nm and 3nm FinFET Nodes SYNOPSYS/Micron Technology
14:30 – 14:50	A-7 Efficient Timing Signoff for 2.5D and 3D Designs: Addressing Inter-Die Complexity at Scale SYNOPSYS/AMD	B-7 Layout Productivity Improvement using Virtuoso Studio Advanced Routing Features Cadence/Qualcomm
14:50 – 15:20	Coffee Break & Ecosystem Pavilion
15:20 – 15:40	A-8 Greatly improve substrate layout for 3DIC design flow & productivity by using both substrate technology file and EDA tool Cadence/IBIDEN	B-8 Shaping the Future of Memory Interfaces: LPDDR5X/6 Combo Subsystem for AI, Security, Automotive, and Beyond Innosilicon
15:40 – 16:00	A-9 Accelerating SOIC 3D-Stacked Advanced Package Design: From Architecture Planning and Optimization to Tapeout SYNOPSYS/Socionext	B-9 Liberty IP Excellence: Building a Robust Verification Framework for automotive IPs Siemens EDA/NXP Semiconductors
16:00 – 16:20	A-10 Achieving 3D-IC Chiplet Security through CoWoS, Starting with PUF-Based OTP and HRoT eMemory Technology	B-10 GDDR Memory for High-Performance AI Inference Rambus/Cadence
16:20 – 17:30	Social Hour

* 講演時間、プログラム等は、変更になる場合がございます。