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Abstract
Chiplet floorplan and bump patterns are critical elements in advanced package and 3DIC designs. 3D floorplan involves determining the placement of the chiplets on the substrate, while the bump pattern refers to the physical layout of the bumps on the substrate that will connect the chiplets to the rest of the system. Each chiplet includes numerous tiles or macros and corresponding bump pattern, which is defined manually. As chiplets become more common in these designs, designers are facing the challenge of creating repeatable and efficient bump patterns and floorplan indentations for each chiplet. To address this challenge, we have developed effective methods to reuse and automate bump creation and floorplan indentation.
In an effort to automate the chiplet floorplan and bump pattern design process, AMD and Synopsys collaborated on the development of Hierarchical Floorplan and Bump Modeling for advanced packaging and 3DIC designs using 3Dblox construct. This approach utilizes 3Dblox modularized library to create fundamental building blocks for the TSMC 3DFabric technology. The chiplet is divided into multiple tiles or physical building blocks. Each tile is then mapped to a corresponding bump pattern in a hierarchical manner. This hierarchical modeling enables optimization of the bump pattern for each tile without affecting neighboring tiles. To formulate the tile-based bump design strategy, the designer must first identify the tiles in the chiplet and map them to the corresponding bump pattern. Multiple bump tiles can be linked to a single physical block. When physical blocks are instantiated, the linked bump tiles are instantiated as well.
By automating floorplan and bump creation from the chiplet boundary hierarchies and die tiling data, designers can create an efficient and reusable bump pattern library with respect to each IP/macro tile. This allows for a more efficient and automated design process, which saves time and minimizes the risk of errors or inconsistencies. This automation process involves creating a hierarchical mapping of the bump pattern for each tile or macro in the chiplet. The hierarchical mapping helps to ensure that the bump pattern is optimized for each tile or macro, while also being consistent across the entire design. Overall, the automation of bump creation and floorplan indentation is an effective way to reuse bump structures, create a repeatable bump pattern, and produce an efficient and automated design process for chiplet-based package and 3DIC designs.
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