Enabling SoC Scaling to GAA Processes with Synopsys Foundation IP

High-performance mobile applications are driving GAA transistor architecture adoption, with hyperscale servers, AI, and high-performance CPUs following closely behind. GAA transistors, along with new power distribution schemes and multi-die-based design, are set to propel semiconductor innovation. However, creating GAA-based SoCs poses many new challenges for designers, including greater variability, complex parasitic extraction, and high modelling accuracy requirements, which can lead to design bottlenecks. This presentation will cover how Synopsys’ collaboration with TSMC on Foundation IP for GAA processes can mitigate some of these challenges. Co-optimization between Synopsys Logic Library IP and Synopsys EDA design flows on GAA technology enables design teams to achieve their demanding performance, power, and area requirements. Synopsys Embedded Memory IP leverages the tunability of GAA technology to ensure a robust design margin and maximize PPA. Together Synopsys Foundation IP and TSMC advanced process technologies using GAA transistors, deliver a uniquely tunable solution to help designers achieve silicon success.