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HPC & 3DFabric Track
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Realizing benefits of Backside Power and Clock on TSMC A16 technology node
Synopsys
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Abstract
TSMC’s A16 backside technology presents significant opportunity for PPA improvements. Power delivery is a growing problem and strengthening can improve IR-Drop of designs.
In this presentation we will present comprehensive data on the impact of PDN on WL, route ability/wire density, cell density, power and thermal effects and potential benefits of clock structures on backside layers due to lower RC.
This will illustrate how to unlock and maximize usage of FS and BS layer stacks to realize full PPA benefits of backside technology."
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Legal Notice
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