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HPC & 3DFabric Track
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Efficient 3D Chiplet Stacking Using TSMC SoIC Technology
Alchip/Synopsys
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Abstract
Multi-die designs allow the integration of heterogeneous dies on different process foundry nodes and for distinct functions, in a single advanced package.
Since 2019, Alchip has successfully taped out dozens of multi-die designs using TSMC’s CoWoS® and InFO family packaging technologies.
Building on this expertise, Alchip is collaborating with Synopsys to expand our design capabilities and exploration-to-signoff flows from 2.5D to 3D multi-die designs that include 3D stacking and hybrid bonding.
This Alchip-Synopsys presentation explores the challenges and key learnings of our collaboration to help designers jump start multi-die design using TSMC SoIC technologies.
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