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Abstract
The high volume of data processing for AI training requires low-latency, power-efficient, and high-bandwidth interconnects, driving the adoption of optical transceivers and near-/co-packaged optics using silicon photonics technology. Synopsys, Ansys, in close collaboration with TSMC have developed an end-to-end multi-die electronic and photonic design flow for TSMC’s Compact Universal Photonic Engine (COUPE) technology to enhance system performance and function. This flow spans unified electronic and photonic design with Synopsys OptoCompiler™ photonic IC design solution, Synopsys 3DIC Compiler platform, and multiphysics analysis with Ansys RedHawk-SC, Totem and RaptorX tools.
The presentation will kick-off with a short historical perspective of the development of optical transceivers, adoption of integrated silicon photonics technology, and associated Photonic Design Automation requirements. After, the presentation will zoom in on the design challenges for TSMC’s Compact Universal Photonic Engine (COUPE) technology and how the Synopsys and Ansys solutions will enable customers to create high performance designs for optical connectivity supporting high performance compute and AI datacenter infrastructures.
In detail, the presenter will discuss the photonic chiplet design, the construction of the overall system with and electrical chiplet stacked onto the photonic chiplet, die to die physical verification, and address the overall electronic photonic circuit level simulation considering high-speed electrical parasitics and thermal effects.
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